unisonic technologies co., ltd m4334 cmos ic www.unisonic.com.tw 1 of 9 copyright ? 2010 unisonic technologies co., ltd qw-r502-441a stereo audio d/a converter 24bits,96khz sampling ? description the utc m4334 is a complete low cost stereo audio digital to analog converter(dac), its contains in terpolation, 1-bit d/a conversion and analog output filtering. the m4334 is based on a 4th order - modulation, where the modulator output controls the reference voltage input to an ultra-liner analog low-pa ss filter. this architecture allows for infinite adjustment of sample rate between 2 khz and 100 khz simply by changing the master clock frequency. the m4334 also contains digital de-em phasis function, operates from a single +5v power supply, for best performance, decoupling capacitors should be located as close to the device package as possible with the smallest capacitor closest, the m4334 requires minimal support circuitry. the m4334 is ideal for dvd players, set-top boxes, svcd players and a/v receivers. ? features * complete stereo dac: includes output analog filter and dac * dynamic range: 96db * thd+n: -88db * multiple sampling frequencies: 16khz to 96khz * low clock jitter sensitivity * single power supply: 5v * filtered line level outputs * on-chip digital de-emphasis * normal or i2s data input formats * 24bits conversion sop-8 ? ordering information ordering number package packing M4334G-S08-R sop-8 tape reel
m4334 cmos ic unisonic technologies co., ltd 2 of 9 www.unisonic.com.tw qw-r502-441a ? pin configurations ? pin description pin no pin name pin type pin description 1 sdata i serial audio data input: two?s complement msb-first serial data is input on this pin. the data is clocked into the m4334 via internal or external sclk, and the channel is determined by lrck. 2 dem/sclk i de-emphasis control and clock input for audio data: used for de-emphasis filter control or external serial clock input. 3 lrck i sample rata clock input: determines which channel is currently being input on the audio serial data input pin. 4 mclk i system clock input: frequency must be 256x, 384x, or 512x the input sample rate in brm and either 128x or 192x the input sample rate in hrm. 5 aoutr o right-channel analog output 6 agnd i ground pin 7 va i power supply pin for the internal control circuits 8 aoutl o left-channel analog output
m4334 cmos ic unisonic technologies co., ltd 3 of 9 www.unisonic.com.tw qw-r502-441a ? block diagram
m4334 cmos ic unisonic technologies co., ltd 4 of 9 www.unisonic.com.tw qw-r502-441a ? absolute maximum rating parameter symbol ratings unit dc power supply v a -0.3~6 v digital input voltage v ind -0.3~ va +0.4 v input current, any pin except supplies i in 10 ma ambient operating temperature t a -55 ~ +125 c storage temperature t stg -65 ~ +150 c note: absolute maximum ratings are those values be yond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device oper ation is not implied. ? recommended operating conditions (note1) parameter symbol range unit dc power supply v a 4.75 ~ 5.5 v note: 1. all voltage values are with respect to the network ground terminal unless otherwise noted. 2. the v out tracks the v ref with additional voltage offset and load regulation. ? electrical characteristics all specifications at 25c,va=+5v, full-scale output sine wave,997hz; mclk=12.288mhz; fs for =48khz, sclk=3.072mhz, measurement bandwidth 10h z to 20khz, unless otherwise specified; f s for hrm=96khz, sclk=6.144mhz, measurement bandwidth 10hz to 40khz, unless otherwise specified. rl=10k , cl=10pf. parameter symbol test conditions min typ max unit power and thermal normal operation 15 19 ma power supply current i a power-down state 40 ua normal operation 75 104 power dissipation p d power-down state 0.2 mw package thermal resistance ja 110 c /w power supply rejection ratio psrr f=1khz 79 db dc accuracy inter channel gain mismatch 0.1 0.4 db gain error 5 % gain drift 100 ppm/c analog output full scale output voltag e 3.25 3.5 3.75 vpp quiescent voltage v q 2.2 vdc max ac-load resistance r l 3 k ? max load capacitance c l 100 pf digital input/output high-level input voltage v ih 2.0 v low-level input voltage v il 0.8 v input leakage current i i(leak) 10 a input capacitance c in 8 pf
m4334 cmos ic unisonic technologies co., ltd 5 of 9 www.unisonic.com.tw qw-r502-441a ? electrical characteristics (cont.) base-rate mode high-rate mode parameter symbol test conditions min typ max min typ max unit ambient operating temperature t opr -40 85 -40 85 c 16-bit , un-weighted 83 91 88 16-bit , a-weighted 86 94 86 94 18 to 24-bit, un-weighted 85 93 90 dynamic range 18 to 24-bit , a-weighted 88 96 88 96 db 16-bit, 0db -86 -70 -86 -80 16-bit, -20db -71 -63 -68 -60 16-bit, -60db -31 -23 -28 -20 18 to 24-bit, 0db -88 -82 -88 -82 18 to 24-bit, -20db -73 -65 -70 -62 total harmonic distortion +noise thd+n 18 to 24-bit, -60db -33 -25 -30 -22 db ? switching charcteristics (t a =-40 to 85 c ;va=4.75v~5.5v; input: logic 0=0v, logic 1=v a , c l =20pf) parameter symbol test conditions min typ max unit input sample rate f s 2 100 khz mclk pulse width high mclk/lrck=512 10 1000 ns mclk pulse width low mclk/lrck=512 10 1000 ns mclk pulse width high mclk/lrck=384 or 192 21 1000 ns mclk pulse width low mclk/lrck=384 or 192 21 1000 ns mclk pulse width high mclk/lrck=256 or 128 31 1000 ns mclk pulse width low mclk/lrck=256 or 128 31 1000 ns external sclk mode lrck duty cycle 40 50 60 % sclk pulse width high t sclkh 20 ns sclk pulse width low t sclkl 20 ns mclk/lrck=512,256 or 384 1 (128) fs ns sclk period t sclkw mclk/lrck=128 or 192 1 (64) fs ns sclk rising to lrck edge delay t slrd 20 ns sclk rising to lrck edge setup time t slrs 20 ns sdata valid to sclk rising setup time t sdlrs 20 ns sclk rising to sdata hold time t sdh 20 ns internal sclk mode lrck duty cycle 50 % sclk period t sclkw 1 sclk ns sclk rising to lrck edge t sclkr tsclkw 2 s sdata valid to sclk rising setup time t sdlrs 1 10 (512) fs + ns sclk rising to sdata hold time t sdh mclk/lrck=128 , 256 or 512 1 +15 (512) fs ns sclk rising to sdata hold time t sdh mclk/lrck=192 or 384 1 15 (384) fs + ns
m4334 cmos ic unisonic technologies co., ltd 6 of 9 www.unisonic.com.tw qw-r502-441a ? timing diagrams inernal sclk mode external sclk mode i 2 s, 16-bit data and internal sclk=32fs if mclk/lrck=128, 256 or 512 i 2 s, up to 24-bit data and internal sclk=48fs if mclk/lrck=192 or 384 i 2 s, up to 24-bit data data valid on rising edge of sclk figure 1. i 2 s data input timing
m4334 cmos ic unisonic technologies co., ltd 7 of 9 www.unisonic.com.tw qw-r502-441a ? typical application circuit
m4334 cmos ic unisonic technologies co., ltd 8 of 9 www.unisonic.com.tw qw-r502-441a ? application consideration the m4334 is a complete low cost stereo digital-to-analog output system contains digital interpolation, fourth-order delta-sigma digital-to-analog conversion, digital de-emphasis and analog low pass filter. the m4334 used the - modulation techniques is to avoid the limitations of resistive laser trimmed dac architectures by using an inherently linear 1-bit dac. the m4334 supports two modes of operation. the devic es operate in base rate mode (brm) when mclk/lrck is 256, 384 or 512 and in high rate mode (hrm) when mclk/lrck is 128 or 192. hrm allows input sample rates up to 100 khz. the m4334 also has the de-emphasis function, the de-emphasis filter is active when the dem/sclk pin is low for 5 consecutive falling edges of lrck, but this func tion is available only in the internal sclk mode. when the m4334 is initially powered-up, the audio outpu ts, aoutl and aoutr, are clamped to agnd. after a sh- ort delay of approximately 1000 sample periods, each ou tput begins to ramp towards its quiescent voltage, vq. app- roximately 10,000 sample cycles later, the outpu ts reach vq and audio output begins. this gradual voltage ramping allows time for the external dc-blocking capacitor to charge to vq, effectively blocking the quiescent dc voltage. to prevent transients at power-down, the device must fi rst enter its power-down state. this is accomplished by rem- oving mclk or lrck. when this occurs, audio output ceases and the internal output buffers are disconnected from aoutl and aoutr. a soft-start current sink is subs tituted in place of aoutl and aoutr which allows the dc-blo- cking capacitors to slowly discharge. once this charge is dissipated, the power to the device may be turned off, and the system is read y for the next power-on. to prevent an audio transient at the next power-on, t he dc-blocking capacitors must fully discharge before turning off the power or exiting the power-down state. if fu ll discharge does not occur, a transient will occur when the audio outputs are initially clamped to agnd . the time that the device must remain in the power-down state is related to the value of the dc-blocking capacitance.
m4334 cmos ic unisonic technologies co., ltd 9 of 9 www.unisonic.com.tw qw-r502-441a ? system clock the m4334 accepts data at standard audio sample rate s including 48, 44.1 and 32 khz in brm and 96, 88.2 and 64 khz in hrm. the lrck chooses the channel and delineation of data, and the sclk clocks audio data into the input data buffer. mclk mclk must be either 256x, 384x or 512x the desired in put sample rate in brm and either 128x or 192x the desired input sample rate in hrm. the lrck frequency is equal to fs, the frequency at which words for each channel are input to the device. the mc lk-to-lrck frequency ratio is detected automatically during the initialization sequence by counting the number of mclk transitions during a single lrck period. internal dividers are set to generate the proper clocks. the mclk, lrck and sclk must be synchronous. table 1 illustrates several standard audio sample rates and the required mclk and lrck frequencies. mclk(mhz) hrm brm lrck(khz) 128x 192x 256x 384x 512x 32 4.0960 6.1440 8. 1920 12.2880 16.3840 44.1 5.6448 8.4672 11. 2896 16.9344 22.5792 48 6.1440 9.2160 12. 2880 18.4320 24.5760 64 8.1920 12.2880 88.2 11.2896 16.9344 96 12.2880 18.4320 table 1. common clock frequencies sclk the sclk controls the shifting of data into the input data buffers. the m4334 supports both internal and external sclk generation modes. internal sclk mode in the internal sclk mode, the sc lk is internally derived and synchronous with mclk and lrck. the sclk/lrck frequency ratio is either 32, 48, or 64 depending up on data format. operation in this mode is identical to operation w- ith an external sclk synchronized with lrck. this mode allows access to the digital de-emphasis function. while the internal sclk mode is provided to allow ac cess to the de-emphasis filter, the internal sclk mode also eliminates possible clock interference from an external sclk. external sclk mode the m4334 will enter the external sclk mode when 16 low to high transitions are detected on the dem/sclk pin during any phase of the lrck period. when this mo de is enabled, the internal sclk mode and de-emphasis filter cannot be accessed. the m4334 will switch to internal sclk mode if no low to high transitions are detected on the dem/sclk pin for 2 cons ecutive frames of lrck. utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.
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